Microelectronic devices including staircase structures, and related memory devices and electronic systems

ABSTRACT

A microelectronic device comprises a stack structure, at least one staircase structure, contact structures, and support structures. The stack structure comprises vertically alternating conductive structures and insulating structures arranged in tiers, each of the tiers individually comprising one of the conductive structures and one of the insulating structures. The at least one staircase structure is within the stack structure and has steps comprising edges of at least some of the tiers. The contact structures are on the steps of the at least one staircase structure. The support structures horizontally alternate with the contact structures in a first horizontal direction and vertically extend through the stack structure. The support structures have oblong horizontal cross-sectional shapes. Additional microelectronic devices, memory devices, and electronic systems are also described.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of U.S. patent application Ser. No.16/667,704, filed Oct. 29, 2019, the disclosure of which is herebyincorporated herein in its entirety by this reference.

TECHNICAL FIELD

The disclosure, in various embodiments, relates generally to the fieldof microelectronic device design and fabrication. More specifically, thedisclosure relates to microelectronic devices including staircasestructures, and to related memory devices and electronic systems.

BACKGROUND

A continuing goal of the microelectronics industry has been to increasethe memory density (e.g., the number of memory cells per memory die) ofmemory devices, such as non-volatile memory devices (e.g., NAND Flashmemory devices). One way of increasing memory density in non-volatilememory devices is to utilize vertical memory array (also referred to asa “three-dimensional (3D) memory array”) architectures. A conventionalvertical memory array includes vertical memory strings extending throughopenings in one or more decks (e.g., stack structures) including tiersof conductive structures and dielectric materials. Each vertical memorystring may include at least one select device coupled in series to aserial combination of vertically-stacked memory cells. Such aconfiguration permits a greater number of switching devices (e.g.,transistors) to be located in a unit of die area (i.e., length and widthof active surface consumed) by building the array upwards (e.g.,vertically) on a die, as compared to structures with conventional planar(e.g., two-dimensional) arrangements of transistors.

Vertical memory array architectures generally include electricalconnections between the conductive structures of the tiers of thedeck(s) (e.g., stack structure(s)) of the memory device and access lines(e.g., word lines) so that the memory cells of the vertical memory arraycan be uniquely selected for writing, reading, or erasing operations.One method of forming such an electrical connection includes formingso-called “staircase” (or “stair step”) structures at edges (e.g.,horizontal ends) of the tiers of the deck(s) of the memory device. Thestaircase structure includes individual “steps” defining contact regionsof the conductive structures, upon which conductive contact structurescan be positioned to provide electrical access to the conductivestructures.

As vertical memory array technology has advanced, enhanced memorydensity has been provided by forming memory devices to exhibit multipledeck (e.g., dual deck) configurations. For example, in one conventionaldual deck configuration, some vertical memory strings are located in anupper deck (e.g., an upper stack structure), and additional verticalmemory strings are located in a lower deck (e.g., a lower stackstructure) underlying the upper deck. The vertical memory strings of theupper deck may be electrically coupled to the additional vertical memorystrings of the lower deck (e.g., by way of conductive interconnectstructures), or the vertical memory strings of the upper deck may beelectrically isolated from the additional vertical memory strings of thelower deck (e.g., by way of an intervening dielectric material).Unfortunately, as feature packing densities have increased and marginsfor formation errors have decreased, conventional deck configurationshave resulted in undesirable defects (e.g., word line thicknessvariations, word line bending, word line bowing, word line contact punchthrough) and current leaks (e.g., word line current leakage) that candiminish desired memory device performance, reliability, and durability.

Accordingly. there remains a need for new microelectronic device (e.g.,memory device, such as 3D NAND Flash memory device) configurationsfacilitating enhanced memory density while alleviating the problems ofconventional microelectronic device configurations, as well as for newelectronic systems including the new microelectronic deviceconfigurations.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified, partial cross-sectional view of amicroelectronic device structure, in accordance with embodiments of thedisclosure.

FIG. 2A is a simplified, partial top-down view of a microelectronicdevice structure, in accordance with embodiments of the disclosure.

FIG. 2B is a simplified, partial cross-sectional view of themicroelectronic device structure shown in FIG. 2A about the line A₁-A₁depicted in FIG. 2A.

FIG. 3A is a simplified, partial top-down view of a microelectronicdevice structure, in accordance with additional embodiments of thedisclosure.

FIG. 3B is a simplified, partial cross-sectional view of themicroelectronic device structure shown in FIG. 3A about the line A₂-A₂depicted in FIG. 3A.

FIG. 4A is a simplified, partial top-down view of a microelectronicdevice structure, in accordance with further embodiments of thedisclosure.

FIG. 4B is a simplified, partial cross-sectional view of themicroelectronic device structure shown in FIG. 4A about the line A₃-A₃depicted in FIG. 4A.

FIG. 5 is a partial cutaway perspective view of a microelectronicdevice, in accordance with embodiments of the disclosure.

FIG. 6 is a schematic block diagram illustrating an electronic system,in accordance with embodiments of the disclosure.

DETAILED DESCRIPTION

The following description provides specific details, such as materialcompositions, shapes, and sizes, in order to provide a thoroughdescription of embodiments of the disclosure. However, a person ofordinary skill in the art would understand that the embodiments of thedisclosure may be practiced without employing these specific details.Indeed, the embodiments of the disclosure may be practiced inconjunction with conventional microelectronic device fabricationtechniques employed in the industry. In addition, the descriptionprovided below does not form a complete process flow for manufacturing amicroelectronic device (e.g., a memory device, such as 3D NAND Flashmemory device). The structures described below do not form a completemicroelectronic device. Only those process acts and structures necessaryto understand the embodiments of the disclosure are described in detailbelow. Additional acts to form a complete microelectronic device fromthe structures may be performed by conventional fabrication techniques.

Drawings presented herein are for illustrative purposes only, and arenot meant to be actual views of any particular material, component,structure, device, or system. Variations from the shapes depicted in thedrawings as a result, for example, of manufacturing techniques and/ortolerances, are to be expected. Thus, embodiments described herein arenot to be construed as being limited to the particular shapes or regionsas illustrated, but include deviations in shapes that result, forexample, from manufacturing. For example, a region illustrated ordescribed as box-shaped may have rough and/or nonlinear features, and aregion illustrated or described as round may include some rough and/orlinear features. Moreover, sharp angles that are illustrated may berounded, and vice versa. Thus, the regions illustrated in the figuresare schematic in nature, and their shapes are not intended to illustratethe precise shape of a region and do not limit the scope of the presentclaims. The drawings are not necessarily to scale. Additionally,elements common between figures may retain the same numericaldesignation.

As used herein, a “memory device” means and includes a microelectronicdevice exhibiting, but not limited to, memory functionality.

As used herein, the terms “vertical,” “longitudinal,” “horizontal,” and“lateral” are in reference to a major plane of a structure and are notnecessarily defined by earth's gravitational field. A “horizontal” or“lateral” direction is a direction that is substantially parallel to themajor plane of the structure, while a “vertical” or “longitudinal”direction is a direction that is substantially perpendicular to themajor plane of the structure. The major plane of the structure isdefined by a surface of the structure having a relatively large areacompared to other surfaces of the structure.

As used herein, features (e.g., regions, structures, devices) describedas “neighboring” one another means and includes features of thedisclosed identity (or identities) that are located most proximate(e.g., closest to) one another. Additional features (e.g., additionalregions, additional structures, additional devices) not matching thedisclosed identity (or identities) of the “neighboring” features may bedisposed between the “neighboring” features. Put another way, the“neighboring” features may be positioned directly adjacent one another,such that no other feature intervenes between the “neighboring”features; or the “neighboring” features may be positioned indirectlyadjacent one another, such that at least one feature having an identityother than that associated with at least one the “neighboring” featuresis positioned between the “neighboring” features. Accordingly, featuresdescribed as “vertically neighboring” one another means and includesfeatures of the disclosed identity (or identities) that are located mostvertically proximate (e.g., vertically closest to) one another.Moreover, features described as “horizontally neighboring” one anothermeans and includes features of the disclosed identity (or identities)that are located most horizontally proximate (e.g., horizontally closestto) one another.

As used herein, spatially relative terms, such as “beneath,” “below,”“lower,” “bottom,” “above,” “upper,” “top,” “front,” “rear,” “left,”“right,” and the like, may be used for ease of description to describeone element's or feature's relationship to another element(s) orfeature(s) as illustrated in the figures. Unless otherwise specified,the spatially relative terms are intended to encompass differentorientations of the materials in addition to the orientation depicted inthe figures. For example, if materials in the figures are inverted,elements described as “below” or “beneath” or “under” or “on bottom of”other elements or features would then be oriented “above” or “on top of”the other elements or features. Thus, the term “below” can encompassboth an orientation of above and below, depending on the context inwhich the term is used, which will be evident to one of ordinary skillin the art. The materials may be otherwise oriented (e.g., rotated 90degrees, inverted, flipped) and the spatially relative descriptors usedherein interpreted accordingly.

As used herein, the singular forms “a,” “an,” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise.

As used herein, “and/or” includes any and all combinations of one ormore of the associated listed items.

As used herein, the term “configured” refers to a size, shape, materialcomposition, orientation, and arrangement of one or more of at least onestructure and at least one apparatus facilitating operation of one ormore of the structure and the apparatus in a pre-determined way.

As used herein, the phrase “coupled to” refers to structures operativelyconnected with each other, such as electrically connected through adirect Ohmic connection or through an indirect connection (e.g., by wayof another structure).

As used herein, the term “substantially” in reference to a givenparameter, property, or condition means and includes to a degree thatone of ordinary skill in the art would understand that the givenparameter, property, or condition is met with a degree of variance, suchas within acceptable tolerances. By way of example, depending on theparticular parameter, property, or condition that is substantially met,the parameter, property, or condition may be at least 90.0 percent met,at least 95.0 percent met, at least 99.0 percent met, at least 99.9percent met, or even 100.0 percent met.

As used herein, “about” or “approximately” in reference to a numericalvalue for a particular parameter is inclusive of the numerical value anda degree of variance from the numerical value that one of ordinary skillin the art would understand is within acceptable tolerances for theparticular parameter. For example, “about” or “approximately” inreference to a numerical value may include additional numerical valueswithin a range of from 90.0 percent to 110.0 percent of the numericalvalue, such as within a range of from 95.0 percent to 105.0 percent ofthe numerical value, within a range of from 97.5 percent to 102.5percent of the numerical value, within a range of from 99.0 percent to101.0 percent of the numerical value, within a range of from 99.5percent to 100.5 percent of the numerical value, or within a range offrom 99.9 percent to 100.1 percent of the numerical value.

FIG. 1 is a simplified, partial cross-sectional view of amicroelectronic device structure 100 of a microelectronic device (e.g.,a semiconductor device; a memory device, such as a 3D NAND Flash memorydevice), in accordance with embodiments of the disclosure. Themicroelectronic device structure 100 may, for example, comprise aportion of a memory device (e.g., a multi-deck 3D NAND Flash memorydevice, such as a dual deck 3D NAND Flash memory device).

As shown in FIG. 1, the microelectronic device structure 100 includes astack structure 102 including a vertically alternating (e.g., in theZ-direction) sequence of conductive structures 104 (e.g., access lineplates, word line plates) and insulating structures 106 arranged intiers 108. Each of the tiers 108 of the stack structure 102 may includeat least one (1) of the conductive structures 104 vertically neighboringat least one of the insulating structures 106. The stack structure 102may include a desired quantity of the tiers 108. For example, the stackstructure 102 may include greater than or equal to ten (10) of the tiers108, greater than or equal to twenty-five (25) of the tiers 108, greaterthan or equal to fifty (50) of the tiers 108, greater than or equal toone hundred (100) of the tiers 108, greater than or equal to one hundredand fifty (150) of the tiers 108, or greater than or equal to twohundred (200) of the tiers 108 of the conductive structures 104 and theinsulating structures 106.

The conductive structures 104 of the tiers 108 of the stack structure102 may be formed of and include at least one electrically conductivematerial, such as a metal (e.g., tungsten (W), titanium (Ti), molybdenum(Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium(Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt(Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum(Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)), an alloy(e.g., a Co-based alloy, an Fe-based alloy, an Ni-based alloy, an Fe-and Ni-based alloy, a Co- and Ni-based alloy, an Fe- and Co-based alloy,a Co- and Ni- and Fe-based alloy, an Al-based alloy, a Cu-based alloy, amagnesium (Mg)-based alloy, a Ti-based alloy, a steel, a low-carbonsteel, a stainless steel), a conductively-doped semiconductor material(e.g., conductively-doped polysilicon, conductively-doped germanium(Ge), conductively-doped silicon germanium (SiGe)), a conductivemetal-containing material (e.g., a conductive metal nitride, aconductive metal silicide, a conductive metal carbide, a conductivemetal oxide), or combinations thereof. In some embodiments, theconductive structures 104 are formed of and include W. Each of theconductive structures 104 may individually include a substantiallyhomogeneous distribution of the at least one conductive material, or asubstantially heterogeneous distribution of the at least one conductivematerial. As used herein, the term “homogeneous distribution” meansamounts of a material do not vary throughout different portions (e.g.,different horizontal portions, different vertical portions) of astructure. Conversely, as used herein, the term “heterogeneousdistribution” means amounts of a material vary throughout differentportions of a structure. Amounts of the material may vary stepwise(e.g., change abruptly), or may vary continuously (e.g., changeprogressively, such as linearly, parabolically) throughout differentportions of the structure. In some embodiments, each of the conductivestructures 104 of each of the tiers 108 of the stack structure 102exhibits a substantially homogeneous distribution of conductivematerial. In additional embodiments, at least one of the conductivestructures 104 of at least one of the tiers 108 of the stack structure102 exhibits a substantially heterogeneous distribution of at least oneconductive material. The conductive structure 104 may, for example, beformed of and include a stack of at least two different conductivematerials. The conductive structures 104 of each of the tiers 108 of thestack structure 102 may each be substantially planar, and may eachexhibit a desired thickness (e.g., vertical height in the Z-direction).

The insulating structures 106 of the tiers 108 of the stack structure102 may be formed of and include at least one dielectric material, suchone or more of at least one dielectric oxide material (e.g., one or moreof a silicon oxide (SiO_(x)), phosphosilicate glass, borosilicate glass,borophosphosilicate glass, fluorosilicate glass, an aluminum oxide(AlO_(x)), a hafnium oxide (HfO_(x)), a niobium oxide (NbO_(x)), atitanium oxide (TiO_(x)), a zirconium oxide (ZrO_(x)), a tantalum oxide(TaO_(x)), and a magnesium oxide (MgO)), at least one dielectric nitridematerial (e.g., a silicon nitride (SiN_(y))), at least one dielectricoxynitride material (e.g., a silicon oxynitride (SiO_(x)N_(y))), and atleast one dielectric carboxynitride material (e.g., a siliconcarboxynitride (SiO_(x)C_(z)N_(y))). Formulae including one or more of“x,” “y,” and “z” herein (e.g., SiO_(x), AlO_(x), HfO_(x), NbO_(x),TiO_(x), SiN_(y), SiO_(x)N_(y), SiO_(x)C_(z)N_(y)) represent a materialthat contains an average ratio of “x” atoms of one element, “y” atoms ofanother element, and “z” atoms of an additional element (if any) forevery one atom of another element (e.g., Si, Al, Hf, Nb, Ti). As theformulae are representative of relative atomic ratios and not strictchemical structure, the insulating structures 106 may comprise one ormore stoichiometric compounds and/or one or more non-stoichiometriccompounds, and values of “x,” “y,” and “z” (if any) may be integers ormay be non-integers. As used herein, the term “non-stoichiometriccompound” means and includes a chemical compound with an elementalcomposition that cannot be represented by a ratio of well-definednatural numbers and is in violation of the law of definite proportions.In some embodiments, the insulating structures 106 are formed of andinclude SiO₂. Each of the insulating structures 106 may individuallyinclude a substantially homogeneous distribution of the at least oneinsulating material, or a substantially heterogeneous distribution ofthe at least one insulating material. In some embodiments, each of theinsulating structures 106 of each of the tiers 108 of the stackstructure 102 exhibits a substantially homogeneous distribution ofinsulating material. In additional embodiments, at least one of theinsulating structures 106 of at least one of the tiers 108 of the stackstructure 102 exhibits a substantially heterogeneous distribution of atleast one insulating material. The insulating structure 106 may, forexample, be formed of and include a stack (e.g., laminate) of at leasttwo different insulating materials. The insulating structures 106 ofeach of the tiers 108 of the stack structure 102 may each besubstantially planar, and may each individually exhibit a desiredthickness.

At least one lower conductive structure 104 of the stack structure 102may be employed as at least one lower select gate (e.g., at least onesource side select gate (SGS)) of the microelectronic device structure100. In some embodiments, a single (e.g., only one) conductive structure104 of a vertically lowermost tier 108 of the stack structure 102 isemployed as a lower select gate (e.g., a SGS) of the microelectronicdevice structure 100. In addition, upper conductive structure(s) 104 ofthe stack structure 102 may be employed as upper select gate(s) (e.g.,drain side select gate(s) (SGDs)) of the microelectronic devicestructure 100. In some embodiments, horizontally neighboring conductivestructures 104 of a vertically uppermost tier 108 of the stack structure102 are employed as upper select gates (e.g., SGDs) of themicroelectronic device structure 100.

With continued reference to FIG. 1, the microelectronic device structure100 may further include at least one staircase structure 110 includingsteps 112 (e.g., contact regions) defined by edges of the tiers 108. Thequantity of steps 112 included in the staircase structure 110 may besubstantially the same as (e.g., equal to) or may be different than(e.g., less than, greater than) the quantity of tiers 108 in each thestack structure 102. As shown in FIG. 1, in some embodiments, the steps112 of the staircase structure 110 are arranged in order, such thatsteps 112 directly horizontally adjacent one another in the X-directioncorrespond to tiers 108 of the stack structure 102 directly verticallyadjacent (e.g., in the Z-direction) one another. In additionalembodiments, the steps 112 of the staircase structure 110 are arrangedout of order, such that at least some steps 112 of the staircasestructure 110 directly horizontally adjacent one another in theX-direction correspond to tiers 108 of stack structure 102 not directlyvertically adjacent (e.g., in the Z-direction) one another.

The microelectronic device structure 100 further includes contactstructures 114 (e.g., access line contact structures, word line contactstructures) physically and electrically contacting the steps 112 of thestaircase structure 110 to provide electrical access to the conductivestructures 104 of the stack structure 102. The contact structures 114may be formed of and include at least one electrically conductivematerial, such as one or more of a metal (e.g., W, Ti, Mo, Nb, V, Hf,Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Jr, Ni, Pa, Pt, Cu, Ag, Au, Al), analloy (e.g., a Co-based alloy, an Fe-based alloy, an Ni-based alloy, anFe- and Ni-based alloy, a Co- and Ni-based alloy, an Fe- and Co-basedalloy, a Co- and Ni- and Fe-based alloy, an Al-based alloy, a Cu-basedalloy, a Mg-based alloy, a Ti-based alloy, a steel, a low-carbon steel,a stainless steel), a conductive metal-containing material (e.g., aconductive metal nitride, a conductive metal silicide, a conductivemetal carbide, a conductive metal oxide), a conductively-dopedsemiconductor material (e.g., conductively-doped Si, conductively-dopedGe, conductively-doped SiGe). Each of the contact structures 114 mayhave substantially the same material composition, or at least one of thecontact structures 114 may have a different material composition than atleast one other of the contact structures 114.

The contact structures 114 may each individually exhibit a desiredgeometric configuration (e.g., dimensions and shape), a desiredhorizontal position (e.g., within the horizontal boundaries of the steps112 of the stack structure 102), and desired horizontal spacing (e.g.,relative to one another, relative to other components of themicroelectronic device structure 100). As described in further detailbelow, the geometric configurations, horizontal positions, andhorizontal spacing of the contact structures 114 may be selected atleast partially based on the geometric configurations, horizontalpositions, and horizontal spacing of other features (e.g., the steps 112of the staircase structure 110, support structures) of themicroelectronic device structure 100. For example, the contactstructures 114 may each individually have a geometric configuration,horizontal position, and horizontal spacing complements the geometricconfigurations, horizontal positions, and horizontal spacing of theother features of the microelectronic device structure 100 so as toimpede (e.g., substantially prevent) tier deformation (e.g., bending,warping, and/or bowing of the conductive structures 104 of the tiers108) and/or tier damage (e.g., contact structure 114 punch through ofconductive structures 104 of the tiers 108 at the steps 112 of thestaircase structure 110) during and/or after the formation of the tiers108 of the stack structure 102 (e.g., by way of “replace gate” or “gatelast” processing acts). Each of the contact structures 114 may exhibitsubstantially the same geometric configuration (e.g., the samedimensions and the same shape), horizontal step position (e.g.,horizontal position within the area of a step 112 associated therewith),and horizontal spacing as each other of the contact structures 114; orat least one of the contact structures 114 may exhibit a differentgeometric configuration (e.g., one or more different dimension(s), adifferent shape), a different horizontal step position, and/or differenthorizontal spacing than at least one other of the contact structures114.

With continued reference to FIG. 1, the microelectronic device structure100 may further include, a routing tier 116 (e.g., a metallization tier)vertically overlying (e.g., in the Z-direction) the contact structures114, and a interconnect tier 118 between the contact structures 114 andthe routing tier 116. The interconnect tier 118 and the routing tier 116may be in electrical communication with the contact structures 114, andmay electrically connect the contact structures 114 (and, hence, theconductive structures 104 of the tiers 108 of the stack structure 102electrically coupled to the contact structures 114) to components of amicroelectronic device (e.g., a memory device) including themicroelectronic device structure 100, as described in further detailbelow. The interconnect tier 118 may include interconnect structures 120(e.g., vertically extending conductive structures) contacting (e.g.,physically contacting, electrically contacting) the contact structures114, and the routing tier 116 may include pad structures 122 (e.g.,horizontally extending conductive structures) contacting (e.g.,physically contacting, electrically contacting) the interconnectstructures 120. In some embodiments, the pad structures 122 areelectrically connected to additional structures and/or devices (e.g.,back end of line (BEOL) devices; control logic devices, such as CMOSdevices) vertically underlying the microelectronic device structure 100.

The interconnect structures 120 and the pad structures 122 may eachindividually be formed of and include at least one electricallyconductive material, such as one or more of a metal (e.g., W, Ti, Mo,Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Jr, Ni, Pa, Pt, Cu, Ag, Au,Al), an alloy (e.g., a Co-based alloy, an Fe-based alloy, an Ni-basedalloy, an Fe- and Ni-based alloy, a Co- and Ni-based alloy, an Fe- andCo-based alloy, a Co- and Ni- and Fe-based alloy, an Al-based alloy, aCu-based alloy, a Mg-based alloy, a Ti-based alloy, a steel, alow-carbon steel, a stainless steel), a conductive metal-containingmaterial (e.g., a conductive metal nitride, a conductive metal silicide,a conductive metal carbide, a conductive metal oxide), aconductively-doped semiconductor material (e.g., conductively-doped Si,conductively-doped Ge, conductively-doped SiGe). In some embodiments,the interconnect structures 120 and the pad structures 122 havesubstantially the same material composition as one another (e.g., areeach formed of and include the same electrically conductivematerial(s)). In additional embodiments, the interconnect structures 120and the pad structures 122 have different material compositions than oneanother (e.g., are formed of and include different electricallyconductive material(s) than one another).

With continued reference to FIG. 1, the microelectronic device structure100 further includes support structures 124 (e.g., support pillars)horizontally between the contact structures 114, and verticallyextending through the stack structure 102. Each of the supportstructures 124 may be formed of and include at least one electricallyconductive material, such as one or more of a metal (e.g., W, Ti, Mo,Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Jr, Ni, Pa, Pt, Cu, Ag, Au,Al), an alloy (e.g., a Co-based alloy, an Fe-based alloy, an Ni-basedalloy, an Fe- and Ni-based alloy, a Co- and Ni-based alloy, an Fe- andCo-based alloy, a Co- and Ni- and Fe-based alloy, an Al-based alloy, aCu-based alloy, a Mg-based alloy, a Ti-based alloy, a steel, alow-carbon steel, a stainless steel), a conductive metal-containingmaterial (e.g., a conductive metal nitride, a conductive metal silicide,a conductive metal carbide, a conductive metal oxide), aconductively-doped semiconductor material (e.g., conductively-doped Si,conductively-doped Ge, conductively-doped SiGe). In some embodiments,the support structures 124 have substantially the same materialcomposition as one another (e.g., are each formed of and include thesame electrically conductive material(s)). In addition, as shown in FIG.1, at least one dielectric liner material 126 may substantially surround(e.g., substantially horizontally and vertically cover) sidewalls ofeach of the support structures 124. The dielectric liner material 126may be horizontally interposed between each of the support structures124 and the tiers 108 (including the conductive structures 104 and theinsulating structure 106 thereof) of the stack structure 102. Thedielectric liner material 126 may be formed of and include one or moreof at least one dielectric oxide material (e.g., one or more of SiO_(x),phosphosilicate glass, borosilicate glass, borophosphosilicate glass,fluorosilicate glass, AlO_(x), HfO_(x), NbO_(x), TiO_(x), ZrO_(x),TaO_(x), and MgO_(x)), at least one dielectric nitride material (e.g.,SiN_(y)), at least one dielectric oxynitride material (e.g.,SiO_(x)N_(y)), at least one dielectric carboxynitride material (e.g.,SiO_(x)C_(z)N_(y)), and amorphous carbon. In some embodiments, thedielectric liner material 126 comprises SiO₂.

The support structures 124 may serve as support features during and/orafter the formation of the conductive structures 104 of the tiers 108 ofthe stack structure 102 using so called “replace gate” or “gate last”processing acts. During replace gate processing, a preliminary stackstructure including a vertically alternating (e.g., in the Z-direction)sequence of the insulating structures 106 and sacrificial structures(e.g., additional insulating structures selectively etchable relative tothe insulating structures 106, such as dielectric nitride structures ifthe insulating structures 106 comprise dielectric oxide structures) maybe subjected to a material removal process to selectively remove (e.g.,selectively exhume) at least a portion (e.g., all, less than all) ofeach the sacrificial structures relative to the insulating structures106. Thereafter, open volumes (e.g., void spaces) formed by the removedportions of the sacrificial structures may be filled with a conductivematerial to form the conductive structures 104. The support structures124 may impede (e.g., prevent) tier deformation (e.g., bending, warping,bowing) and/or tier damage (e.g., undesirable tier punch through) duringand/or after the selective removal of the sacrificial structures.

The support structures 124 may individually be horizontally interposedbetween horizontally neighboring contact structures 114, and mayindividually vertically extend through the tiers 108 of the stackstructure 102 at or horizontally proximate the steps 112 of thestaircase structure 110 to one or more structures of one or more tiers(e.g., a source tier) vertically underlying the stack structure 102. Asshown in FIG. 1, in some embodiments, the support structures 124horizontally alternate with the contact structures 114 in a firsthorizontal direction (e.g., the X-direction). The support structures 124may be located within horizontal boundaries of the staircase structure110, and, optionally, may also be located outside the horizontalboundaries of the staircase structure 110 (e.g., some of the supportstructures 124 may be located outside of but proximate to the horizontalboundaries of the staircase structure 110).

The support structures 124 may each individually exhibit a desiredgeometric configuration (e.g., dimensions and shape), a desiredhorizontal position (e.g., within the horizontal boundaries staircasestructure 110 of the stack structure 102), and desired horizontalspacing (e.g., relative to one another, relative the contact structures114, relative to other components of the microelectronic devicestructure 100). As described in further detail below, the geometricconfigurations, horizontal positions, and horizontal spacing of thesupport structures 124 may be selected at least partially based on thegeometric configurations, horizontal positions, and horizontal spacingof other components (e.g., the steps 112 of the staircase structure 110,the contact structures 114) of the microelectronic device structure 100.For example, the support structures 124 may each individually have ageometric configuration, horizontal position, and horizontal spacingpermitting the support structure 124 to vertically extend (e.g., in theZ-direction) through the stack structure 102 and impede (e.g.,substantially prevent) tier deformation (e.g., bending, warping, and/orbowing of the conductive structures 104 of the tiers 108) and/or tierdamage (e.g., contact structure 114 punch through of conductivestructures 104 of the tiers 108 at the steps 112 of the staircasestructure 110) during and/or after the formation of the tiers 108 of thestack structure 102 (e.g., by way of “replace gate” or “gate last”processing acts). Each of the support structures 124 may exhibitsubstantially the same geometric configuration (e.g., the samedimensions and the same shape), horizontal step position (e.g.,horizontal position within the area of one or more steps 112 associatedtherewith), and horizontal spacing as each other of the supportstructures 124; or at least one of the support structures 124 mayexhibit a different geometric configuration (e.g., one or more differentdimension(s), a different shape), a different horizontal step position,and/or different horizontal spacing than at least some other of thesupport structures 124.

With continued reference to FIG. 1, the microelectronic device structure100 may further include an isolation material 128 on or over the stackstructure 202. The isolation material 128 may cover the staircasestructure 110 of the stack structure 102, and may surround surfaces ofthe contact structures 114, the interconnect structures 120, the padstructures 122, the support structures 124, and the dielectric linermaterial 126. The isolation material 128 may exhibit a substantiallynon-planar lower vertical boundary complementary to the topography of atleast the stack structure 202 (including the staircase structure 110thereof) thereunder.

The isolation material 128 may be formed of and include at least onedielectric material, such as one or more of at least one dielectricoxide material (e.g., one or more of SiO_(x), phosphosilicate glass,borosilicate glass, borophosphosilicate glass, fluorosilicate glass,AlO_(x), HfO_(x), NbO_(x), TiO_(x), ZrO_(x), TaO_(x), and MgO_(x)), atleast one dielectric nitride material (e.g., SiN_(y)), at least onedielectric oxynitride material (e.g., SiO_(x)N_(y)), and at least onedielectric carboxynitride material (e.g., SiO_(x)C_(z)N_(y)). Theisolation material 128 may include a substantially homogeneousdistribution or a substantially heterogeneous distribution of the atleast one dielectric material. In some embodiments, the isolationmaterial 128 exhibits a substantially homogeneous distribution ofdielectric material. In further embodiments, the isolation material 128exhibits a substantially heterogeneous distribution of at least onedielectric material. The isolation material 128 may, for example, beformed of and include a stack (e.g., laminate) of at least two differentdielectric materials. In some embodiments, the isolation material 128 isformed of and includes SiO₂.

As previously described, the microelectronic device structure 100 may beformed to exhibit different configurations of at least the contactstructures 114 and the support structures 124 thereof that impede (e.g.,substantially prevent) tier deformation and/or tier damage during and/orafter the formation of the tiers 108 of the stack structure 102 (e.g.,by way of “replace gate” or “gate last” processing acts). By way ofnon-limiting example, FIGS. 2A through 4B are simplified top-down (FIGS.2A, 3A, and 4A) and partial cross-sectional (FIGS. 2B, 3B, and 4B) viewsof different microelectronic device structure configurations, inaccordance with embodiments of the disclosure. The microelectronicdevice structures described below with reference to FIGS. 2A through 4Bmay each individually exhibit features (e.g., structures, materials,regions) substantially similar to the previously-described features(e.g., the stack structure 102, including the tiers 108 of theconductive structures 104 and the insulative structures 106; thestaircase structure 110, including the steps 112; the contact structures114; the support structures 124; the dielectric liner material 126; theinterconnect structures 120; the pad structures 122; the isolationmaterial 128) of the microelectronic device structure 100. However, themicroelectronic device structures described below with reference toFIGS. 2A through 4B may exhibit different horizontal configurations(e.g., different horizontal shapes, different horizontal sizes,different horizontal positions) of contact structures and supportstructures thereof that may be employed to impede tier deformationand/or tier damage during and/or after the formation of tiers(corresponding and substantially similar to the tiers 108 (FIG. 1))thereof. Throughout FIGS. 2A through 4B and the associated descriptionbelow, features (e.g., structures, materials, regions) functionallysimilar to features of the microelectronic device structure 100 (FIG. 1)are referred to with similar reference numerals incremented by 100. Notall features previously described with reference FIG. 1 are shown inFIGS. 2A through 4B. However, unless described otherwise below, it willbe understood that features (and feature configurations) included in themicroelectronic device structure 100 previously described with referenceto FIG. 1 are also included in the microelectronic device structuresdescribed below with reference to FIGS. 2A through 4B. In addition, toavoid repetition, not all features shown in FIGS. 2A through 4B aredescribed in detail herein. Rather, unless described otherwise below, inFIGS. 2A through 4B, a feature designated by a reference numeral that isa 100 increment of the reference numeral of a previously describedfeature (whether the previously described feature is first describedbefore the present paragraph, or is first described after the presentparagraph) will be understood to be substantially similar to thepreviously-described feature.

FIG. 2A is a partial, top-down view of a microelectronic devicestructure 200, in accordance with an embodiment of the disclosure. FIG.2B is a simplified, partial cross-sectional view of a portion of themicroelectronic device structure 200 shown in FIG. 2A about the lineA₁-A₁ depicted in FIG. 2A. For clarity and ease of understanding of thedrawings and related description, not all features (e.g., structures,materials, regions) of the microelectronic device structure 200 depictedin one of FIGS. 2A and 2B are depicted the other of FIGS. 2A and 2B. Forexample, some features of the microelectronic device structure 200vertically overlying or vertically underlying other features of themicroelectronic device structure 200 are not shown in each of FIGS. 2Aand 2B so as to provide a clearer view of the other features.

Referring to FIG. 2A, a stack structure 202 (corresponding to the stackstructure 102 (FIG. 1)) of the microelectronic device structure 200 maybe partitioned by slots 230. The slots 230 may extend in parallel in afirst horizontal direction (e.g., the X-direction), and may partition(e.g., divide) the stack structure 202 in a second horizontal direction(e.g., the Y-direction) orthogonal to the first horizontal directioninto multiple blocks 232. The slots 230 may vertically extendsubstantially completely through the stack structure 202. The slots 230may, for example, be employed to form the conductive structures 204(FIG. 2B) (corresponding to the conductive structures 104 (FIG. 1)) ofthe stack structure 202 through so-called “replace gate” or “gate last”processing acts. As shown in FIG. 2A, the slots 230 may be filled withisolation material 228.

The contact structures 214 may each individually be provided at adesired horizontal location (e.g., in the X-direction and theY-direction) on or over one of the steps 212 of the microelectronicdevice structure 200. As shown in FIG. 2A, in some embodiments, eachcontact structure 214 is individually substantially horizontallycentered on one of the steps 212 of the microelectronic device structure200. For example, for each block 232 of the microelectronic devicestructure 200, the contact structures 214 associated with (e.g., withinhorizontal boundaries of) the block 232 may be substantiallyhorizontally centered in the X-direction and the Y-direction on thesteps 212 of the staircase structure 210 of the block 232. In additionalembodiments, one or more of the contact structures 214 are individuallyhorizontally offset (e.g., in the X-direction and/or in the Y-direction)from a horizontal center of the step 212 associated therewith. Forexample, for one or more of the blocks 232 of the microelectronic devicestructure 200, at least one (e.g., all, less than all) of the contactstructures 214 associated with the block 232 may be horizontally offsetin the Y-direction from a horizontal center of the step 212 on which thecontact structure 214 is located. As another example, for one or more ofthe blocks 232 of the microelectronic device structure 200, at least one(e.g., all, less than all) of the contact structures 214 associated withthe block 232 may be horizontally offset in the X-direction from ahorizontal center of the step 212 on which the contact structure 214 islocated.

The contact structures 214 may each individually exhibit a desiredhorizontal cross-sectional shape. As shown in FIG. 2A, in someembodiments, each of the contact structures 214 exhibits a substantiallycircular horizontal cross-sectional shape. In additional embodiments,one or more (e.g., each) of the contact structures 214 exhibits anon-circular cross-sectional shape, such as one more of an oblongcross-sectional shape, an elliptical cross-sectional shape, a squarecross-sectional shape, a rectangular cross-sectional shape, a tear dropcross-sectional shape, a semicircular cross-sectional shape, a tombstonecross-sectional shape, a crescent cross-sectional shape, a triangularcross-sectional shape, a kite cross-sectional shape, and an irregularcross-sectional shape. In addition, each of the contact structures 214may exhibit substantially the same horizontal cross-sectional dimensions(e.g., substantially the same horizontal diameter), or at least one ofthe contact structures 214 may exhibit one or more different horizontalcross-sectional dimensions (e.g., a different horizontal diameter) thanat least one other of the contact structures 214. In some embodiments,all of the contact structures 214 exhibit substantially the samehorizontal cross-sectional dimensions.

With continued reference to FIG. 2A, some of the contact structures 214on the steps 212 of the stack structure 202 of the microelectronicdevice structure 200 may be horizontally aligned with one another. Forexample, at least some (e.g., all) contact structures 214 horizontallyneighboring one another (e.g., in the X-direction) within horizontalboundaries of an individual (e.g., single) block 232 of themicroelectronic device structure 200 (and, hence, on steps 212 atdifferent vertical positions than one another within the block 232 ofthe microelectronic device structure 200) may be substantially alignedwith one another (e.g., in the Y-direction). In some embodiments,horizontal centers of all contact structures 214 associated with (e.g.,within horizontal boundaries of) the same block 232 as one another aresubstantially aligned with one another in the Y-direction, as depictedby the phantom line B i-Bi horizontally extending in the X-direction inFIG. 2A. In additional embodiments, horizontal centers of at least some(e.g., all) contact structures 214 associated with (e.g., withinhorizontal boundaries of) the same block 232 as one another are offsetfrom (e.g., unaligned with) one another in the Y-direction. As anotherexample, at least some (e.g., all, less than all) contact structures 214horizontally neighboring one another in the Y-direction (and, hence, onsteps 212 at substantially the same vertical position as one anotherwithin different blocks 232 of the microelectronic device structure 200)may be substantially aligned with one another in the X-direction. Inaddition, referring to FIG. 2B, the contact structures 214 may eachindividually be substantially horizontally centered in the Y-directionabout horizontal centers of the interconnect structure 220 and the padstructure 222 operatively associated therewith (e.g., electricallyconnected thereto). In additional embodiments, a horizontal center ofone or more (e.g., each) of the contact structures 214 may behorizontally offset in the Y-direction from a horizontal center of oneor more of the interconnect structure 220 and the pad structure 222operatively associated therewith (e.g., electrically connected thereto).

With returned reference to FIG. 2A, the support structures 224 may eachindividually be provided at a desired horizontal location (e.g., in theX-direction and the Y-direction) relative to the contact structures 214.Support structures 224 associated with (e.g., within horizontalboundaries of) an individual block 232 of the microelectronic devicestructure 200 may horizontally alternate with and be spaced apart fromthe contact structures 214 associated with the block 232 in theX-direction. In some embodiments, for each block 232 of themicroelectronic device structure 200, each support structure 224associated with the block 232 is substantially horizontally centered inthe X-direction about adjacent boundaries of horizontally neighboringsteps 212; and is substantially horizontally centered in the Y-directionabout a horizontal centerline of the steps 212 of the block 232. Inadditional embodiments, for one or more blocks 232 of themicroelectronic device structure 200, at least one support structure 224associated with the block 232 is horizontally offset in the X-directionfrom adjacent boundaries of horizontally neighboring steps 212. Forexample, a majority (e.g., greater than 50 percent, such as greater thanor equal 60 percent, greater than or equal to 70 percent, or greaterthan or equal to 80 percent) of the support structure 224 may be locatedwithin horizontal boundaries of one of the horizontally neighboringsteps 212, and a minority (e.g., less than 50 percent, such as less thanor equal to 40 percent, less than or equal to 30 percent, or less thanor equal to 20 percent) of the support structure 224 may be locatedwithin horizontal boundaries of the other of the horizontallyneighboring steps 212. In further embodiments, for one or more blocks232 of the microelectronic device structure 200, a horizontal center ofat least one support structure 224 associated with the block 232 ishorizontally offset in the Y-direction from the horizontal centerline ofthe steps 212 of the block 232. For example, the support structure 224may be located more proximate one slot 230 horizontally neighboring afirst side of the block 232 than another slot 230 horizontallyneighboring a second, opposing side of the block 232.

As shown in FIG. 2A, the support structures 224 may each individuallyexhibit an oblong horizontal cross-sectional shape. The oblonghorizontal cross-section shape may, for example, include two (2)generally semicircular regions, and a generally rectangular regionhorizontally extending between the two (2) generally semicircularregions. In additional embodiments, one or more of the supportstructures 224 exhibits a different oblong horizontal cross-sectionalshape (e.g., an ovular horizontal cross-sectional shape, a rectangularhorizontal cross-sectional shape, a tombstone horizontal cross-sectionalshape, a kite cross-sectional shape, an irregular cross-sectionalshape). A horizontal dimension (e.g., width) of the support structures224 in a first horizontal direction (e.g., the X-direction) may be lessthan another horizontal dimension (e.g., length) of the supportstructures 224 is a second horizontal dimension (e.g., the Y-direction).For example, between horizontally neighboring contact structures 214associated with (e.g., within horizontal boundaries of) an individualblock 232 of the microelectronic device structure 200, a single (e.g.,only one) support structure 224 may horizontally extend in theY-direction across a majority (e.g., greater than 50 percent, such asgreater than or equal 60 percent, greater than or equal to 70 percent,or greater than or equal to 80 percent) of the horizontal dimension(e.g., length) in the Y-direction of horizontally neighboring steps 212contacting the horizontally neighboring contact structures 214. Each ofthe support structures 224 may exhibit substantially the same horizontalcross-sectional dimensions (e.g., substantially the same width in theX-direction, substantially the same length in the Y-direction), or atleast one of the support structures 224 may exhibit one or moredifferent horizontal cross-sectional dimensions (e.g., a different widthin the X-direction, a different length in the Y-direction) than at leastone other of the support structures 224. In some embodiments, all of thesupport structures 224 exhibit substantially the same horizontalcross-sectional dimensions.

With continued reference to FIG. 2A, some of the support structures 224of the microelectronic device structure 200 may be horizontally alignedwith one another. For example, at least some (e.g., all) supportstructures 224 horizontally neighboring one another (e.g., in theX-direction) within horizontal boundaries of an individual (e.g.,single) block 232 of the microelectronic device structure 200 may besubstantially aligned with one another (e.g., in the Y-direction). Insome embodiments, horizontal centers of all support structures 224associated with (e.g., within horizontal boundaries of) the same block232 as one another are substantially aligned with one another in theY-direction, as depicted by the phantom line B₁-B₁ horizontallyextending in the X-direction in FIG. 2A. As shown in FIG. 2A, in someembodiments, the support structures 224 associated with the same block232 as one another are also substantially aligned (e.g., in theY-direction) with the contact structures 214 associated with block 232.In additional embodiments, horizontal centers of at least some (e.g.,all) contact structures 214 associated with (e.g., within horizontalboundaries of) the same block 232 as one another are offset from (e.g.,unaligned with) one another in the Y-direction and/or are offset fromhorizontal centers of at least some contact structures 214 in theY-direction. As another example, at least some (e.g., all, less thanall) support structures 224 horizontally neighboring one another in theY-direction (and, hence, within different blocks 232 of themicroelectronic device structure 200 than one another) may besubstantially aligned with one another in the X-direction.

FIG. 3A is a partial, top-down view of a microelectronic devicestructure 300, in accordance with an embodiment of the disclosure. FIG.3B is a simplified, partial cross-sectional view of a portion of themicroelectronic device structure 300 shown in FIG. 3A about the lineA₂-A₂ depicted in FIG. 3A. For clarity and ease of understanding of thedrawings and related description, not all features (e.g., structures,materials, regions) of the microelectronic device structure 300 depictedin one of FIGS. 3A and 3B are depicted the other of FIGS. 3A and 3B. Forexample, some features of the microelectronic device structure 300vertically overlying or vertically underlying other features of themicroelectronic device structure 300 are not shown in each of FIGS. 3Aand 3B so as to provide a clearer view of the other features.

The contact structures 314 may each individually be provided at adesired horizontal location (e.g., in the X-direction and theY-direction) on or over one of the steps 312 of the microelectronicdevice structure 300. As shown in FIG. 3A, for one or more (e.g., each)of the blocks 332 of the microelectronic device structure 300,horizontal positions in the Y-direction of at least some (e.g., each) ofthe contact structures 314 associated with (e.g., within horizontalboundaries of) the block 332 may be different than horizontal positionsin the Y-direction of at least some (e.g., each) other of the contactstructures 314 associated with the block 332. For example, the contactstructures 314 associated with an individual (e.g., single) block 332may progressively shift from horizontal positions relatively moreproximate an individual slot 330 horizontally neighboring the block 332to other horizontal positions relatively more distal from the individualslot 330 (e.g., other horizontal positions reality more proximatehorizontal centers in the Y-direction of the steps 312 of the block332). In some embodiments, contact structures 314 contacting relativelyvertically higher steps 312 of an individual block 332 are positionedrelatively horizontally closer to an individual slot 330 horizontallyneighboring the block 332 than are contact structures 314 contactingrelatively vertically lower steps 312 of the block 332. Each contactstructure 314 associated with an individual block 332 of themicroelectronic device structure 300 may have a different horizontalposition in the Y-direction than each other contact structure 314associated with the individual block 332, or at least one (but less thanall) contact structure 314 associated with the individual block 332 mayhave substantially the same horizontal position in the Y-direction as atleast one (but less than all) other contact structure 314 associatedwith the individual block 332. In addition, for one or more (e.g., each)of the blocks 332 of the microelectronic device structure 300, thecontact structures 314 associated with the block 332 may besubstantially horizontally centered in the X-direction on the steps 312of the block 332. In additional embodiments, for one or more (e.g.,each) of the blocks 332 of the microelectronic device structure 300, atleast one (e.g., all, less than all) of the contact structures 314associated with the block 332 is horizontally offset in the X-directionfrom a horizontal center of the step 312 on which the contact structure314 is located.

The contact structures 314 may each individually exhibit a desiredhorizontal cross-sectional shape and desired horizontal cross-sectionaldimensions. The horizontal cross-sectional shapes and horizontalcross-sectional dimensions of the contact structures 314 may besubstantially similar to the horizontal cross-sectional shapes and thehorizontal cross-sectional dimensions of the contact structures 214previously described with reference to FIG. 2A.

With continued reference to FIG. 3A, at least some (e.g., all) contactstructures 314 associated with an individual (e.g., single) block 332 ofthe microelectronic device structure 300 may be horizontally offset fromone another in the Y-direction. For example, horizontal centers ofcontact structures 314 horizontally neighboring one another in theX-direction within horizontal boundaries of the block 332 (and, hence,on steps 312 at different vertical positions than one another within theblock 332) may be offset from one another in the Y-direction, asdepicted by the phantom line B₂-B₂ horizontally extending in theX-direction in FIG. 3A. In additional embodiments, horizontal centers ofat least some (but less than all) contact structures 314 associated withthe same block 332 as one another are substantially aligned with oneanother in the Y-direction. As shown in FIG. 3A, at least one supportstructure 324 associated with an individual block 332 is substantiallyaligned in the Y-direction with at least two horizontally neighboring(e.g., in the X-direction) contact structures 314 associated with block332. In addition, at least some (e.g., all, less than all) contactstructures 314 horizontally neighboring one another in the Y-direction(and, hence, on steps 312 at substantially the same vertical position asone another within different blocks 332 of the microelectronic devicestructure 300) may be substantially aligned with one another in theX-direction. In addition, referring to FIG. 3B, a horizontal center ofone or more (e.g., each) of the contact structures 314 may behorizontally offset in the Y-direction from a horizontal center of oneor more of the interconnect structure 320 and the pad structure 322operatively associated therewith (e.g., electrically connected thereto).In some embodiments, the horizontal dimensions (e.g., lengths) of thepad structures 322 are elongated in the Y-direction relative to thehorizontal dimensions (e.g., lengths) of the pad structures 222 (FIG.2B) in the Y-direction to accommodate the horizontal positions in theY-direction of the contact structures 314.

With returned reference to FIG. 3A, the support structures 324 may eachindividually be provided at a desired horizontal location (e.g., in theX-direction and the Y-direction) relative to the contact structures 314.As shown in FIG. 3A, individual blocks 332 of the microelectronic devicestructure 300 may include pairs of the support structures 324horizontally neighboring one another in the Y-direction. The pairs ofsupport structures 324 may horizontally alternate with and be spacedapart from the contact structures 314 associated with the block 232 inthe X-direction. In some embodiments, for each individual block 332 ofthe microelectronic device structure 300, support structures 324horizontally neighboring one another in the Y-direction aresubstantially horizontally centered in the X-direction about adjacentboundaries of horizontally neighboring steps 312. In additionalembodiments, for one or more blocks 332 of the microelectronic devicestructure 300, at least some support structures 324 horizontallyneighboring one another in the Y-direction are horizontally offset inthe X-direction from adjacent boundaries of horizontally neighboringsteps 312. For example, majorities (e.g., greater than 50 percent, suchas greater than or equal 60 percent, greater than or equal to 70percent, or greater than or equal to 80 percent) of the supportstructures 324 may be located within horizontal boundaries of one of thehorizontally neighboring steps 312, and minorities (e.g., less than 50percent, such as less than or equal to 40 percent, less than or equal to30 percent, or less than or equal to 20 percent) of the supportstructures 324 may be located within horizontal boundaries of the otherof the horizontally neighboring steps 312. As shown in FIG. 3A, forindividual blocks 332 of the microelectronic device structure 300,horizontal centers of support structures 324 associated with the block332 are horizontally offset in the Y-direction from a horizontalcenterline of the steps 312 of the block 332.

The support structures 324 may each individually exhibit a desiredhorizontal cross-sectional shape. As shown in FIG. 3A, in someembodiments, each of the support structures 324 exhibits a substantiallycircular horizontal cross-sectional shape. In additional embodiments,one or more (e.g., each) of the support structures 324 exhibits anon-circular cross-sectional shape, such as one more of an oblongcross-sectional shape, an elliptical cross-sectional shape, a squarecross-sectional shape, a rectangular cross-sectional shape, a tear dropcross-sectional shape, a semicircular cross-sectional shape, a tombstonecross-sectional shape, a crescent cross-sectional shape, a triangularcross-sectional shape, a kite cross-sectional shape, and an irregularcross-sectional shape. In addition, each of the support structures 324may exhibit substantially the same horizontal cross-sectional dimensions(e.g., substantially the same horizontal diameter), or at least one ofthe support structures 324 may exhibit one or more different horizontalcross-sectional dimensions (e.g., a different horizontal diameter) thanat least one other of the support structures 324. In some embodiments,all of the support structures 324 exhibit substantially the samehorizontal cross-sectional dimensions.

With continued reference to FIG. 3A, some of the support structures 324of the microelectronic device structure 300 may be horizontally alignedwith one another. For example, at least some (e.g., all) supportstructures 324 horizontally neighboring one another in the Y-directionwithin horizontal boundaries of an individual block 332 of themicroelectronic device structure 200 may be substantially aligned withone another in the X-direction. As another example, at least some (e.g.,all) support structures 324 horizontally neighboring one another in theX-direction within horizontal boundaries of an individual block 332 ofthe microelectronic device structure 300 may be substantially alignedwith one another in the Y-direction. In addition, at least some (e.g.,all, less than all) support structures 324 horizontally neighboring oneanother in the Y-direction and within different blocks 332 of themicroelectronic device structure 300 than one another may besubstantially aligned with one another in the X-direction.

FIG. 4A is a partial, top-down view of a microelectronic devicestructure 400, in accordance with an embodiment of the disclosure. FIG.4B is a simplified, partial cross-sectional view of a portion of themicroelectronic device structure 400 shown in FIG. 4A about the lineA₂-A₂ depicted in FIG. 4A. For clarity and ease of understanding of thedrawings and related description, not all features (e.g., structures,materials, regions) of the microelectronic device structure 400 depictedin one of FIGS. 4A and 4B are depicted the other of FIGS. 4A and 4B. Forexample, some features of the microelectronic device structure 400vertically overlying or vertically underlying other features of themicroelectronic device structure 400 are not shown in each of FIGS. 4Aand 4B so as to provide a clearer view of the other features.

As shown in FIG. 4A, the microelectronic device structure 400 may besubstantially similar to the microelectronic device structure 300 (FIG.3A), except that individual blocks 432 of the microelectronic devicestructure 400 may include multiple contact structures 414 at the samehorizontal position in the X-direction as one another. For example,individual blocks 432 of the microelectronic device structure 400 mayinclude pairs of the contact structures 414 horizontally neighboring oneanother in the Y-direction. The pairs of contact structures 414 mayhorizontally alternate in the X-direction with pairs of supportstructures 424 horizontally neighboring one another in the Y-direction.In addition, horizontal positions in the Y-direction of at least some(e.g., each) of the contact structures 414 associated with the block 432may be different than horizontal positions in the Y-direction of atleast some (e.g., each) other of the contact structures 414 associatedwith the block 432. For example, the contact structures 414 associatedwith an individual block 432 may progressively shift from horizontalpositions relatively more proximate slots 430 horizontally neighboringthe block 432 to other horizontal positions relatively more distal fromthe slots 430 (e.g., other horizontal positions reality more proximatehorizontal centers in the Y-direction of the steps 412 of the block432). In some embodiments, pairs of contact structures 414 horizontallyneighboring one another in the Y-direction and contacting relativelyvertically higher steps 412 of an individual block 432 are positionedrelatively horizontally closer to slots 430 horizontally neighboring theblock 432 than are other pairs of contact structures 414 horizontallyneighboring one another in the Y-direction and contacting relativelyvertically lower steps 412 of the block 432. In addition, for one ormore (e.g., each) of the blocks 432 of the microelectronic devicestructure 400, the contact structures 414 associated with the block 432may be substantially horizontally centered in the X-direction on thesteps 412 of the block 432. In additional embodiments, for one or more(e.g., each) of the blocks 432 of the microelectronic device structure400, at least one (e.g., all, less than all) of the contact structures414 associated with the block 432 is horizontally offset in theX-direction from a horizontal center of the step 412 on which thecontact structure 414 is located.

With continued reference to FIG. 4A, at least some (e.g., all) contactstructures 414 associated with an individual (e.g., single) block 432 ofthe microelectronic device structure 400 may be horizontally offset fromone another in the Y-direction. For example, horizontal centers ofcontact structures 414 horizontally neighboring one another in theX-direction within horizontal boundaries of the block 432 (and, hence,on steps 412 at different vertical positions than one another within theblock 432) may be offset from one another in the Y-direction, asdepicted by the phantom lines B₂-B₂ and the additional phantom linesC₃-C₃ horizontally extending in the X-direction in FIG. 4A. Inadditional embodiments, horizontal centers of at least some (but lessthan all) contact structures 414 associated with the same block 432 asone another are substantially aligned with one another in theY-direction. As shown in FIG. 4A, at least two support structures 424associated with an individual block 432 are substantially aligned in theY-direction with horizontally neighboring (e.g., in the X-direction)support structures 424 associated with block 432. In addition, at leastsome (e.g., all, less than all) contact structures 414 horizontallyneighboring one another in the Y-direction may be substantially alignedwith one another in the X-direction. In addition, referring to FIG. 4B,horizontal centers of contact structures 414 on the same step 412 as oneanother (and, hence, at the same vertical position in the Z-direction asone another) may each be horizontally offset in the Y-direction from ahorizontal center of one or more of the interconnect structure 420 andthe pad structure 422 operatively associated therewith (e.g.,electrically connected thereto). In some embodiments, the horizontaldimensions (e.g., lengths) of the pad structures 422 are elongated inthe Y-direction relative to the horizontal dimensions (e.g., lengths) ofthe pad structures 222 (FIG. 2B) in the Y-direction to accommodate thehorizontal positions in the Y-direction of the contact structures 414.

FIG. 5 illustrates a partial cutaway perspective view of a portion of amicroelectronic device 501 (e.g., a memory device, such as a dual deck3D NAND Flash memory device) including a microelectronic devicestructure 500. The microelectronic device structure 500 may besubstantially similar to one of the microelectronic device structures100, 200, 300, 400 previously described with reference to FIGS. 1through 4B. For example, as shown in FIG. 5, the microelectronic devicestructure 500 may include a stack structure 502 including tiers 508 ofvertically alternating (e.g., in the Z-direction) conductive structuresand insulative structures, and horizontally divided (e.g., in theY-direction) into multiple blocks 532 horizontally separated (e.g., inthe Y-direction) from one another by slots 530; staircase structures 510having steps 512 defined by edges of the tiers 508; contact structures514 connected (e.g., physically connected, electrically connected) tothe steps 512 of the staircase structures 510; and support structures524 vertically extending through the stack structure 502.

The microelectronic device 501 further includes a source tier 534underlying the stack structure 502. The source tier 534 includes asource structure 536 (e.g., a source plate) and discrete conductivestructures 538 (e.g., discrete conductive island structures)horizontally separated (e.g., in the X-direction and in the Y-direction(FIG. 2A) perpendicular to the X-direction) from the source structure536 and from one another. The source structure 536 and the discreteconductive structures 538 may be located at substantially the samevertical position (e.g., in the Z-direction) within the microelectronicdevice 501 as one another. At least one dielectric material may behorizontally interposed between (e.g., in the X-direction and in theY-direction) the discrete conductive structures 538 and may also behorizontally interposed between the discrete conductive structures 538and the source structure 536. Put another way, the dielectric materialmay horizontally intervene between and separate horizontally neighboringdiscrete conductive structures 538 of the source tier 534, and may alsohorizontally intervene between and separate the source structure 536 andthe discrete conductive structures 538 of the source tier 534.

The source structure 536 and the discrete conductive structures 538 mayeach individually be formed of and include at least one electricallyconductive material, such as one or more of a metal (e.g., W, Ti, Mo,Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Cu, Ag, Au,Al), an alloy (e.g., a Co-based alloy, an Fe-based alloy, an Ni-basedalloy, an Fe- and Ni-based alloy, a Co- and Ni-based alloy, an Fe- andCo-based alloy, a Co- and Ni- and Fe-based alloy, an Al-based alloy, aCu-based alloy, a Mg-based alloy, a Ti-based alloy, a steel, alow-carbon steel, a stainless steel), a conductive metal-containingmaterial (e.g., a conductive metal nitride, a conductive metal silicide,a conductive metal carbide, a conductive metal oxide), aconductively-doped semiconductor material (e.g., conductively-doped Si,conductively-doped Ge, conductively-doped SiGe). In some embodiments,the source structure 536 and the discrete conductive structures 538 havesubstantially the same material composition as one another. Put anotherway, the source structure 536 and the discrete conductive structures 538may be formed of and include the same electrically conductive materialas one another. For example, the source structure 536 and the discreteconductive structures 538 may be formed (e.g., substantiallysimultaneously formed) by patterning (e.g., using a predeterminedreticle configuration) the electrically conductive material.

The discrete conductive structures 538 of the source tier 534 may belocated vertically below (e.g., in the Z-direction) and in physicalcontact with the support structures 524 of the microelectronic devicestructure 500. Accordingly, the discrete conductive structures 538 maybe located horizontally proximate (e.g., in the X-direction and theY-direction) and vertically below (e.g., in the Z-direction) the contactstructures 514 on the steps 512 of the stack structure 502 of themicroelectronic device structure 500. For example, the discreteconductive structures 538 may individually be positioned horizontallybetween and vertically below horizontally neighboring contact structures514. The discrete conductive structures 538 may be located withinhorizontal boundaries of the staircase structures 510, and, optionally,may also be located outside of the horizontal boundaries of thestaircase structures 510 (e.g., some of the discrete conductivestructures 538 may be located outside of but proximate to the horizontalboundaries of the staircase structures 510).

The discrete conductive structures 538 may each individually exhibit anydesired geometric configuration (e.g., dimensions and shape) andspacing. In some embodiments, one or more (e.g., each) of the discreteconductive structures 538 exhibits a generally quadrilateral (e.g.,generally rectangular, generally square) shape. Each of the discreteconductive structures 538 may exhibit substantially the same geometricconfiguration (e.g., the same dimensions and the same shape) andhorizontal spacing (e.g., in the X-direction, in the Y-direction) aseach other of the discrete conductive structures 538, or at least someof the discrete conductive structures 538 may exhibit a differentgeometric configuration (e.g., one or more different dimensions, adifferent shape) and/or different horizontal spacing than at least someother of the discrete conductive structures 538.

As shown in FIG. 5, the microelectronic device 501 may further includestrings 540 of memory cells 542 vertically coupled to each other inseries, data lines 544 (e.g., bit lines), access lines 546, and selectlines 548. The strings 540 of the memory cells 542 extend vertically andorthogonal to conductive lines and tiers (e.g., the data lines 544, thesource tier 534, the tiers 508 of the stack structure 502, the accesslines 546, the select lines 548) of the microelectronic device 501, andthe contact structures 514 may electrically couple components to eachother as shown (e.g., the access lines 546 and the select lines 548 tothe tiers 508 of the stack structure 502 of the microelectronic devicestructure 500).

With continued reference to FIG. 5, the microelectronic device 501 mayalso include a control unit 550 (e.g., a control device) positionedvertically below the strings 540 of memory cells 542, which may includeone or more of string driver circuitry, pass gates, circuitry forselecting gates, circuitry for selecting conductive lines (e.g., thedata lines 544, the access lines 546, the select lines 548, additionaldata lines, additional access lines, additional select lines), circuitryfor amplifying signals, and circuitry for sensing signals. In someembodiments, the control unit 550 is at least partially (e.g.,substantially) positioned within horizontal boundaries (e.g., in theX-direction and the Y-direction) of a horizontal area occupied by thestrings 540 of memory cells 542. The control unit 550 may, for example,be electrically coupled to the data lines 544, the source structure 536of the source tier 534, the access lines 546, and the select lines 548.In some embodiments, the control unit 550 includes CMOS (complementarymetal-oxide-semiconductor) circuitry. In such embodiments, the controlunit 550 may be characterized as having a “CMOS under Array” (“CuA”)configuration.

Thus, in accordance with embodiments of the disclosure, amicroelectronic device comprises a stack structure, at least onestaircase structure, contact structures, and support structures. Thestack structure comprises vertically alternating conductive structuresand insulating structures arranged in tiers, each of the tiersindividually comprising one of the conductive structures and one of theinsulating structures. The at least one staircase structure is withinthe stack structure and has steps comprising edges of at least some ofthe tiers. The contact structures are on the steps of the at least onestaircase structure. The support structures horizontally alternate withthe contact structures in a first horizontal direction and verticallyextend through the stack structure. The support structures have oblonghorizontal cross-sectional shapes.

Furthermore, in accordance with additional embodiments of thedisclosure, a microelectronic device comprises a stack structure, atleast one staircase structure, contact structures, and supportstructures. The stack structure comprises tiers each comprising at leastone conductive structure and at least one insulating structurevertically adjacent the at least one conductive structure. The at leastone staircase structure has steps comprising horizontal ends of at leastsome of the tiers. The contact structures are in physical contact withthe steps of the staircase structure. At least some of the contactstructures are horizontally offset from one another in a firstdirection. The support structures are horizontally interposed betweenthe contact structures in a second direction orthogonal to the firstdirection and vertically extend through the stack structure.

Moreover, in accordance with further embodiments of the disclosure, amemory device comprises a stack structure, a staircase structure, asource tier, contact structures, support structures, data lines, anarray of vertically extending strings of memory cells, conductive lines,and a control device. The stack structure comprises verticallyalternating conductive structures and insulating structures arranged intiers, each of the tiers individually comprising at least one of theconductive structures and at least one of the insulating structures. Thestaircase structure has steps comprising edges of at least some of thetiers of the stack structure. The source tier underlies the stackstructure and comprises a source plate, and discrete conductivestructures horizontally separated from one another and the source plateby a dielectric material. The contact structures are on the steps of thestaircase structure. The support structures are horizontally between thecontact structures and vertically extend through the stack structure tothe discrete conductive structures of the source tier. The data linesoverly the stack structure. The array of vertically extending strings ofmemory cells extend through the stack structure and are electricallyconnected to the source plate and the data lines. The conductive linesare electrically connected to the contact structures. The control devicevertically underlies the source tier and is within horizontal boundariesof the array of vertically extending strings of memory cells, thecontrol device electrically coupled to the source plate, the data lines,and the conductive lines.

Microelectronic device structures (e.g., the microelectronic devicestructures 100, 200, 300, 400 previously described with reference toFIGS. 1 through 4B) and microelectronic devices (e.g., themicroelectronic device 501 previously described with reference to FIG.5) in accordance with embodiments of the disclosure may be used inembodiments of electronic systems of the disclosure. For example, FIG. 6is a block diagram of an illustrative electronic system 600 according toembodiments of disclosure. The electronic system 600 may comprise, forexample, a computer or computer hardware component, a server or othernetworking hardware component, a cellular telephone, a digital camera, apersonal digital assistant (PDA), portable media (e.g., music) player, aWi-Fi or cellular-enabled tablet such as, for example, an IPAD® orSURFACE® tablet, an electronic book, a navigation device, etc. Theelectronic system 600 includes at least one memory device 602. Thememory device 602 may comprise, for example, an embodiment of one ormore of a microelectronic device structure (e.g., at least one of themicroelectronic device structures 100, 200, 300, 400 previouslydescribed with reference to FIGS. 1 through 4B) and a microelectronicdevice (e.g., the microelectronic device 501 previously described withreference to FIG. 5) previously described herein. The electronic system600 may further include at least one electronic signal processor device604 (often referred to as a “microprocessor”). The electronic signalprocessor device 604 may, optionally, include an embodiment of one ormore of a microelectronic device structure (e.g., at least one of themicroelectronic device structures 100, 200, 300, 400 previouslydescribed with reference to FIGS. 1 through 4B) and a microelectronicdevice (e.g., the microelectronic device 501 previously described withreference to FIG. 5). While the memory device 602 and the electronicsignal processor device 604 are depicted as two (2) separate devices inFIG. 6, in additional embodiments, a single (e.g., only one)memory/processor device having the functionalities of the memory device602 and the electronic signal processor device 604 is included in theelectronic system 600. In such embodiments, the memory/processor devicemay include one or more of a microelectronic device structure (e.g., atleast one of the microelectronic device structures 100, 200, 300, 400previously described with reference to FIGS. 1 through 4B) and amicroelectronic device (e.g., the microelectronic device 501 previouslydescribed with reference to FIG. 5) previously described herein. Theelectronic system 600 may further include one or more input devices 606for inputting information into the electronic system 600 by a user, suchas, for example, a mouse or other pointing device, a keyboard, atouchpad, a button, or a control panel. The electronic system 600 mayfurther include one or more output devices 608 for outputtinginformation (e.g., visual or audio output) to a user such as, forexample, one or more of a monitor, a display, a printer, an audio outputjack, and a speaker. In some embodiments, the input device 606 and theoutput device 608 may comprise a single touchscreen device that can beused both to input information to the electronic system 600 and tooutput visual information to a user. The input device 606 and the outputdevice 608 may communicate electrically with one or more of the memorydevice 602 and the electronic signal processor device 604.

Thus, in accordance with embodiments of the disclosure, an electronicsystem comprises an input device, an output device, a processor deviceoperably coupled to the input device and the output device, and a memorydevice operably coupled to the processor device. The memory devicecomprises at least one microelectronic device structure comprising astack structure comprising tiers each comprising an electricallyconductive structure and a dielectric structure vertically neighboringthe electrically conductive structure; a staircase structure within thestack structure and exhibiting steps comprising edges of at least someof the tiers; a source tier vertically below the stack structure andcomprising: a source structure, and discrete conductive structureselectrically isolated from one another and the source structure;conductive contact structures on the steps of the staircase structure;and conductive support pillars having oblong horizontal cross-sectionalshapes horizontally alternating with the conductive contact structuresand vertically extending through the stack structure at the staircasestructure to the discrete conductive structures of the source tier.

The structures (e.g., the microelectronic device structures 100, 200,300, 400), devices (e.g., the microelectronic device 501), and systems(e.g., the electronic device 600) of the disclosure advantageouslyfacilitate one or more of improved performance, reliability, anddurability, lower costs, increased miniaturization of components,improved pattern quality, and greater packaging density as compared toconventional structures, conventional devices, and conventional systems.By way of non-limiting example, the configurations of the contactstructures (e.g., the contact structures 114, 214, 314, 414 of thedisclosure previously described with reference to FIGS. 1 through 4B)and the support structures (e.g., the support structures 124, 224, 324,424) of the disclosure may reduce the risk of undesirable word linedeformations (e.g., bending, warping, bowing), undesirable word linedamage (e.g., word line contact punch through), and undesirable wordline current leakage as compared to conventional contact structureconfigurations and support structure configurations.

While the disclosure is susceptible to various modifications andalternative forms, specific embodiments have been shown by way ofexample in the drawings and have been described in detail herein.However, the disclosure is not limited to the particular formsdisclosed. Rather, the disclosure is to cover all modifications,equivalents, and alternatives falling within the scope of the followingappended claims and their legal equivalents.

1. A microelectronic device, comprising: a stack structure comprisingtiers each comprising at least one conductive structure and at least oneinsulating structure vertically adjacent the at least one conductivestructure; a staircase structure having steps comprising horizontal endsof at least some of the tiers; contact structures in physical contactwith the steps of the staircase structure, at least some of the contactstructures horizontally offset from one another in a first direction;and support structures horizontally interposed between the contactstructures in a second direction orthogonal to the first direction andvertically extending through the stack structure.
 2. The microelectronicdevice of claim 1, wherein each of the contact structures ishorizontally offset in the first direction from each other of thecontact structures.
 3. The microelectronic device of claim 1, furthercomprising a filled slot vertically extending through the stackstructure and dividing the stack structure into two blocks.
 4. Themicroelectronic device of claim 3, wherein the contact structures areprogressively horizontally spaced farther away from the filled slot inthe first direction, from relatively vertically higher steps of thestaircase structure to relatively vertically lower steps of thestaircase structure.
 5. The microelectronic device of claim 1, whereinat least two of the support structures horizontally neighbor one anotherin the first direction and horizontally intervene between at least twoof the contact structures horizontally neighboring one another in thesecond direction.
 6. The microelectronic device of claim 1, wherein atleast some of the steps of the staircase structure individually have atleast two of the contact structures thereon, the at least two of thecontact structures horizontally neighboring one another in the seconddirection.
 7. A memory device, comprising: a stack structure comprisingvertically alternating conductive structures and insulating structuresarranged in tiers, each of the tiers individually comprising at leastone of the conductive structures and at least one of the insulatingstructures; a staircase structure having steps comprising edges of atleast some of the tiers of the stack structure; a source tier underlyingthe stack structure and comprising: a source plate; and discreteconductive structures horizontally separated from one another and thesource plate by a dielectric material; contact structures on the stepsof the staircase structure; support structures horizontally between thecontact structures and vertically extending through the stack structureto the discrete conductive structures of the source tier; data linesoverlying the stack structure; an array of vertically extending stringsof memory cells extending through the stack structure and electricallyconnected to the source plate and the data lines; conductive lineselectrically connected to the contact structures; and a control devicevertically underlying the source tier and within horizontal boundariesof the array of vertically extending strings of memory cells, thecontrol device electrically coupled to the source plate, the data lines,and the conductive lines.
 8. The memory device of claim 7, wherein:support structures have oblong horizontal cross-sectional shapes; thesupport structures horizontally alternate with the contact structures ina first horizontal direction; and horizontal centers of the supportstructures are substantially aligned with horizontal centers of thecontact structures in a second horizontal direction orthogonal to thefirst horizontal direction.
 9. The memory device of claim 7, whereinpairs of the support structures horizontally intervene betweenhorizontally neighboring contact structures of the contact structures.10. The memory device of claim 7, wherein: the contact structures arehorizontally spaced apart from one another in a first horizontaldirection; and horizontal centers of the contact structures are offsetfrom one another in a second horizontal direction perpendicular to thefirst horizontal direction.
 11. The memory device of claim 7, whereinpairs of the contact structures horizontally alternate with pairs of thesupport structures.
 12. The memory device of claim 7, wherein thesupport structures each individually comprise: an electricallyconductive pillar structure; and a dielectric liner materialsubstantially covering sidewalls of the electrically conductive pillarstructure.
 13. The memory device of claim 7, wherein the discreteconductive structures and the source plate of the source tier areelectrically isolated from one another.
 14. The memory device of claim7, wherein the control device comprises CMOS circuitry.
 15. Anelectronic system, comprising: an input device; an output device; aprocessor device operably coupled to the input device and the outputdevice; and a memory device operably coupled to the processor device andcomprising at least one microelectronic device structure comprising: astack structure comprising tiers each comprising an electricallyconductive structure and a dielectric structure vertically neighboringthe electrically conductive structure; a staircase structure within thestack structure and exhibiting steps comprising edges of at least someof the tiers; a source tier vertically below the stack structure andcomprising: a source structure; and discrete conductive structureselectrically isolated from one another and the source structure; andconductive contact structures on the steps of the staircase structure;and conductive support pillars having oblong horizontal cross-sectionalshapes horizontally alternating with the conductive contact structuresand vertically extending through the stack structure at the staircasestructure to the discrete conductive structures of the source tier. 16.The electronic system of claim 15, wherein the memory device comprises amulti-deck 3D NAND Flash memory device.
 17. The microelectronic deviceof claim 1, wherein: the stack structure is partitioned into blocksseparated from one another by dielectric-filled slots, thedielectric-filled slots dividing the staircase structure into relativelysmaller staircase structures confined within horizontal areas of theblocks; and at least one two of the contact structures neighboring oneanother in the first direction and within horizontal areas of differentones of the relatively smaller staircase structures than one another arespaced closer together in the first direction than at least two other ofthe contact structures neighboring one another in the first directionand within the horizontal areas of the different ones of the relativelysmaller staircase structures than one another.
 18. The microelectronicdevice of claim 17, wherein lower ends of the at least two of thecontact structures are positioned relatively vertically higher withinthe stack structure than lower ends of the at least two other of thecontact structures.
 19. The microelectronic device of claim 17, whereinat least two of the support structures neighboring one another in thefirst direction and within the horizontal areas of the different ones ofthe relatively smaller staircase structures than one another are spacedapart from one another in the first direction by substantially the samedistance as at least two other of the support structures neighboring oneanother in the first direction and within the horizontal areas of thedifferent ones of the relatively smaller staircase structures than oneanother.
 20. The microelectronic device of claim 19, wherein: the atleast two of the support structures are horizontally interposed betweenthe at least one two of the contact structures and the at least twoother of the contact structures in the second direction; and the atleast one two of the contact structures are horizontally interposedbetween the at least two of the support structures and the at least twoother of the support structures in the second direction.